The present invention relates to semiconductor packages, and more particularly, to a multi-chip semiconductor package with a heat dissipating structure having a chip receiving cavity, so as to improve overall heat dissipating efficiency and miniaturize the profile of the semiconductor package.
With the continuing development of the packaging technology, semiconductor devices become available with various forms of packages. In particular, BGA (ball grid array) semiconductor packages having high density of input/output (I/O) connections and the self-alignment function become a main stream of products suitably to be used in electronic devices due to preferable characteristics of high memory capacity, high processing speed and low profile in appearance.
In order to achieve high functionality and performances of electronic products, besides the foregoing preferably characteristics of the BGA semiconductor packages for use in the electronic products, it is greatly critical to increase the layout density of semiconductor devices on a main board or to enhance the circuit integration of semiconductor chips encapsulated in the semiconductor devices. However, since the increased layout of the semiconductor devices leads to enlargement in usage area of the main board, it is not favorable in response to a low profile trend of electronic product development. As for the integration enhancement of the semiconductor chips, it may be restricted in extent by the current technology, and also undesirably causes increase in packaging costs. Therefore, an effective solution is to mount two or more chips in a single packaging device with multiply provision of integrated circuit density, memory capacity and processing speed.
A conventional stacked-chip or multi-chip-module (MCM) semiconductor package is made by firstly mounting multiple chips on a chip carrier and subsequently performing an encapsulating process. FIGS. 1A and 1B illustrate cross-sectional views of the stacked-chip semiconductor package and the multi-chip-module semiconductor package, respectively. As shown in the drawings, the semiconductor package 1 includes a chip carrier 10 such as a substrate or a tape, for mounting a plurality of semiconductor chips 11 with different dimensions thereon; a plurality of conductive elements 12 such as gold wires or solder bumps for electrically connecting the chips 11 to the chip carrier 10; and an encapsulant 13 for encapsulating the chips 11. The stacked-chip or MCM semiconductor package 1 is therefore characterized in electrically bonding the chips 11 of different dimensions onto the chip carrier 10 in a stack or flip-chip manner to be subsequently encapsulated by the encapsulant 13. However, such a multi-chip semiconductor package 1 is dimensionally higher than normal, and occupies more area as mounted on an external printed circuit board; this is not ideal for the low profile development of electronic products.
In addition, a semiconductor package having multiple chips is also provided with high density of electronic elements and electronic circuits, and thus a large amount of heat would be generated in operation of the multi-chip semiconductor package. In this case, if the heat cannot be dissipated effectively and rapidly, it would seriously damage the functionality and lifetime of the chips. Therefore, a BGA package provided with a heat spreader is accordingly developed. U.S. Pat. No. 5,397,921 entitled xe2x80x9cTAB GRID ARRAYxe2x80x9d discloses a cavity down BGA semiconductor package for improving heat dissipating efficiency and electrical functions thereof Referring to FIG. 2, such a semiconductor package 1xe2x80x2 includes a substrate 10xe2x80x2 formed at a central position with an opening 102 dimensionally larger than a semiconductor chip; a heat spreader 14 mounted on the substrate 10xe2x80x2, and formed with a downwardly-opened chip receiving cavity 142 corresponding in position to the opening 102 of the substrate 10xe2x80x2; a semiconductor chip 11xe2x80x2 accommodated in the chip receiving cavity 142; a plurality of conductive elements 12xe2x80x2 for electrically connecting the chip 11xe2x80x2 to the substrate 10xe2x80x2; a plurality of solder balls 15; and an encapsulant 13xe2x80x2 for encapsulating the chip 11xe2x80x2. This semiconductor package 1xe2x80x2 is different from a normal BGA package by disposing the chip 11xe2x80x2 with its circuit surface (not shown) facing downwardly in the chip receiving cavity 142, and electrically connecting the circuit surface of the chip 11xe2x80x2 directly to the substrate 10xe2x80x2. This significantly shortens the electrical transmitting distance from the chip 11xe2x80x2 to the outermost solder balls 15, and thereby reduces the interference of electric inductance. The semiconductor package 1xe2x80x2 is further advantageous of having good heat dissipating efficiency with the provision of the heat spreader 14 for rapidly dissipating heat produced by the chip 11xe2x80x2 and efficiently cooling down the chip 11xe2x80x2.
However, the foregoing cavity down BGA package structure can only be incorporated with one semiconductor chip, which is not suitably applicable for a multi-chip semiconductor package. Therefore, it is tremendously desired to find out a solution for the heat dissipation problem of the multi-chip semiconductor package that is highly integrated with electronic circuits and electronic elements.
A primary objective of the present invention is to provide a multi-chip semiconductor package, in which a heat dissipating structure is formed with a chip receiving cavity for receiving at least one semiconductor chip therein so as to enhance heat dissipation efficiency.
Another objective of the invention is to provide a multi-chip semiconductor package for reducing overall dimensions of the fabricated packaging product.
A further objective of the invention is to provide a multi-chip semiconductor package, which can be made by current fabricating equipment without using the costly flip-chip technology.
In accordance with the foregoing and other objectives, the present invention proposes a multi-chip semiconductor package, comprising: a chip carrier having at least one opening for receiving a semiconductor chip therein; a heat dissipating structure formed with a chip receiving cavity corresponding in position above the opening of the chip carrier, and a plurality of through holes for interconnecting the chip receiving cavity and the opening of the chip carrier and for allowing gold wires and an encapsulating resin to pass through the through holes; a first and a second semiconductor chips attached to surfaces of the heat dissipating structure, and received in the chip receiving cavity and the opening of the chip carrier respectively; a plurality of gold wires for electrically connecting the chips to the chip carrier; and an encapsulant for encapsulating the chips and the gold wires.
Since the chips are respectively in direct contact with the heat dissipating structure, heat generated by the chips can be rapidly dissipated via the heat dissipating structure with the provision of the shortest heat transmitting pathway; this therefore significantly improves heat dissipating efficiency of the semiconductor package. Besides, compared to a conventional stacked-chip semiconductor structure, this invention with the chips being accommodated in the chip receiving cavity and the opening of the chip carrier, allows internal elements to be more compactly arranged in the semiconductor package, thereby making the packaging space optimally utilized. This is beneficially applicable to a multi-chip structure in favor of high memory capacity without undesirably increasing package dimensions, and is therefore preferable for low profile development of electronic products.